The present invention relates to a parallel computer system composed of a plurality of processors and a host processor.
The data transmission between the processors of a parallel computer system according to the prior art are accomplished by two methods: one--for data transmission between two processors being synchronized with each other; the other--for data transmission between two processors being left asynchronous. In the second method, more specifically, the individual processors are controlled so as to perform so-called "data flow type operations", in which each operation is not started in a processor before all data necessary for the operation arrive at the processor. According to the first method an overhead for synchronizing two processors for data transmission is a problem. That is, one processor is frequently interrupted for the synchronism by another so that each using efficiency of each processor is degraded. According to the second method, on the other hand, the difficulty of the first method can be eliminated to some extent. Since, however, an operation cannot be started before all necessary data is prepared, the steps of an operation--data transmission--wait are sequential, and the overheads for the steps of the data transmission and wait are still left.
Another third method has also been proposed for data transmission without any synchronization of the processors (e.g., Japanese Patent Laid-Open No. 49464/1985). In this example, a processor sends not only data to be transmitted but also addresses of instructions requiring the former. Each time the receive processor receives the data, the execution of an instruction is interrupted, and a flag indicating arrival of the necessary data is added to the instruction which is in an address accompanying the data received. According to this third method, the interruption of the instruction execution for the above-specified processing is performed upon each data receipt, thus obstructing the desired high-speed operations.